QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 152

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.51
6.2.52
6.2.53
6.2.54
152
ODTC - On Die Termination Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
SMVREFC - System Memory VREF Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
DQSMT - DQS Master Timing
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register can be locked by the Global RCOMP Lock bit (GBRCOMPCTL[31]).
RCVENMT - RCVENOUTB Master Timing
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains the margining controls and status indicators for the RCVENOUTB
signals in both channels. This register can be locked by the Global RCOMP Lock bit
(GBRCOMPCTL[31]).
5:4
3:0
Bit
7
6
Access
R/W/L
R/W/L
R/W/L
RO
Default
Value
00b
0b
0b
8h
Reserved
Differential Receive Strobe Control:
Reserved
Reserved
0: Disabled
1: Enabled
0/0/0/MCHBAR
284-287h
00000000h
R/W/L; RO
32 bits
0/0/0/MCHBAR
2A0h
08h
R/W/L; RO
8 bits
0/0/0/MCHBAR
2F4-2F5h
0007h
R/W/L
16 bits
0/0/0/MCHBAR
2F8-2FBh
0000070Fh
R/W/L; RO
32 bits
Description
Device 0 Memory Mapped I/O Register
Datasheet