QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 127

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
Datasheet
21:20
19:18
17:17
Bit
Access
R/W
R/W
RO
Default
Value
10b
00b
0b
Back-to-Back Read-Write Command Spacing:
This field determines the number of turnaround clocks between
the read command and a subsequent write command.
The minimum spacing of commands is calculated based on the
formula:
DDR2 = BL/2 + TA + 1
(
This is derived as follows:
DDR2 = CL + BL/2 + TA (wr-rd) - WL
DDR2 = CL + BL/2 + TA - CL + 1
)
BL is the burst length and is set to 8
TA is the required read to write DQ turnaround on the bus. Can
be set to 1,2,3, 4 CK
CL is CAS Latency
The bigger turnarounds are used in large configurations, where
the difference in total channel delay between the fastest and
slowest DIMM is large.
Back-to-Back Write Command Spacing:
This field controls the turnaround time on the DQ bus for WR-
WR sequence to different ranks in one channel.
The minimum spacing of commands is calculated based on the
formula
DDR2 = BL/2 + TA
Encoding
00
01
10
11
The bigger turnarounds are used in large configurations, where
the difference in total channel delay between the fastest and
slowest DIMM is large.
Reserved
Encoding
00
01
10
11
(Sheet 3 of 4)
2 turnaround clocks on DQ
1 turnaround clocks on DQ
0 turnaround clocks on DQ
Reserved
Turnaround
BL4 CMD
Spacing
7
6
5
4
Description
BL8 CMD
Spacing
9
8
7
6
6
5
4
BL8 CMD Spacing
127