QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 252

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

7.1.34
252
DCTL - Device Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command register.
15:12
11:11
10:8
7:5
Bit
4
3
2
1
0
Access
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
Default
Value
000b
000b
0h
0b
0b
0b
0b
0b
0b
Reserved
Reserved
Reserved
Max Payload Size (MPS):
Packets (TLP). As a receiver, the Device must handle TLPs as
large as the set value; as transmitter, the Device must not
generate TLPs exceeding the set value.
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to
support compliance testing.
Reserved
Unsupported Request Reporting Enable (URRE):
When set, Unsupported Requests will be reported.
Reporting of error messages received by Root Port is controlled
exclusively by Root Control register.
Fatal Error Reporting Enable (FERE):
When set fatal errors will be reported. For a Root Port, the
reporting of fatal errors is internal to the root. No external
ERR_FATAL message is generated.
Non-Fatal Error Reporting Enable (NFERE):
When set non-fatal errors will be reported. For a Root Port, the
reporting of non-fatal errors is internal to the root. No external
ERR_NONFATAL message is generated. Uncorrectable errors can
result in degraded performance.
Correctable Error Reporting Enable (CERE):
When set correctable errors will be reported. For a Root Port, the
reporting of correctable errors is internal to the root. No external
ERR_CORR message is generated.
000:128B max supported payload for Transaction Layer
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
0/1/0/PCI
A8-A9h
0000h
R/W; RO
16 bits
Description
Datasheet