D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 107

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
2.8
The H8S/2600 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.
Reset State
The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes
low, all current processing stops and the CPU enters the reset state. All interrupts are masked
in the reset state. Reset exception handling starts when the RES signal changes from low to
high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
Program Execution State
In this state the CPU executes program instructions in sequence.
Bus-Released State
In a product which has a bus master other than the CPU, such as a direct memory access
controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when
the bus has been released in response to a bus request from a bus master other than the CPU.
While the bus is released, the CPU halts operations.
Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further
details, refer to section 22, Power-Down Modes.
Processing States
Rev. 3.00 Mar 17, 2006 page 55 of 926
REJ09B0283-0300
Section 2 CPU

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