D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 311

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

This LSI has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4
channels.
7.1
DMAS260A_010020020400
Selectable as short address mode or full address mode
16-Mbyte address space can be specified directly
Byte or word can be set as the transfer unit
Activation sources: internal interrupt, external request, auto-request (depending on transfer
mode)
Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts
Serial communication interface (SCI_0, SCI_1) transmission complete interrupt, reception
complete interrupt
A/D converter conversion end interrupt
External request
Auto-request
Module stop mode can be set
Short address mode
Maximum of 4 channels can be used
Dual address mode or single address mode can be selected
In dual address mode, one of the two addresses, transfer source and transfer destination, is
specified as 24 bits and the other as 16 bits
In single address mode, transfer source or transfer destination address only is specified as
24 bits
In single address mode, transfer can be performed in one bus cycle
Choice of sequential mode, idle mode, or repeat mode for dual address mode and single
address mode
Full address mode
Maximum of 2 channels can be used
Transfer source and transfer destination addresses as specified as 24 bits
Choice of normal mode or block transfer mode
Features
Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 259 of 926
Section 7 DMA Controller (DMAC)
REJ09B0283-0300