D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 398

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 8 EXDMA Controller
8.3.5
EDACR specifies address register incrementing/decrementing and use of the repeat area function.
Bit
15
14
13
Rev. 3.00 Mar 17, 2006 page 346 of 926
REJ09B0283-0300
Bit Name
SAT1
SAT0
SARIE
EXDMA Address Control Register (EDACR)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Source Address Update Mode
These bits specify incrementing/decrementing
of the transfer source address (EDSAR). When
an external device with DACK is designated as
the transfer source in single address mode, the
specification by these bits is ignored.
0X: Fixed
10: Incremented (+1 in byte transfer, +2 in word
11: Decremented (–1 in byte transfer, –2 in
Source Address Repeat Interrupt Enable
When this bit is set to 1, in the event of source
address repeat area overflow, the IRF bit is set
to 1 and the EDA bit cleared to 0 in EDMDR,
and transfer is terminated. If the EDIE bit in
EDMDR is 1 when the IRF bit in EDMDR is set
to 1, an interrupt request is sent to the CPU.
When used together with block transfer mode, a
source address repeat interrupt is requested at
the end of a block-size transfer. If the EDA bit is
set to 1 in EDMDR for the channel on which
transfer is terminated by a source address
repeat interrupt, transfer can be resumed from
the state in which it ended. If a source address
repeat area has not been designated, this bit is
ignored.
0: Source address repeat interrupt is not
1: When source address repeat area overflow
requested
occurs, the IRF bit in EDMDR is set to 1 and
an interrupt is requested
transfer)
word transfer)