D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 83

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

2.4.2
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
2.4.3
EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC
instructions. When these instructions except for the STC instruction is executed, all interrupts
including NMI will be masked for three states after execution is completed.
Bit
7
6 to 3
2
1
0
Program Counter (PC)
Extended Register (EXR)
Bit Name
T
—
I2
I1
I0
SP (ER7)
Initial Value
0
All 1
1
1
1
Figure 2.8 Stack
R/W
R/W
—
R/W
R/W
R/W
Description
Trace Bit
When this bit is set to 1, a trace exception is
started each time an instruction is executed.
When this bit is cleared to 0, instructions are
executed in sequence.
Reserved
These bits are always read as 1.
These bits designate the interrupt mask level (0
to 7). For details, refer to section 5, Interrupt
Controller.
Rev. 3.00 Mar 17, 2006 page 31 of 926
Stack area
Free area
REJ09B0283-0300
Section 2 CPU