D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 416

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 EXDMA Controller
EDA Bit in EDMDR: The EDA bit in EDMDR is written to by the CPU to control enabling and
disabling of data transfer, but may be cleared automatically by the EXDMAC due to the DMA
transfer status. There are also periods during transfer when a 0-write to the EDA bit by the CPU is
not immediately effective.
Conditions for EDA bit clearing by the EXDMAC include the following:
When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA
transfer period. In block transfer mode, since a block-size transfer is carried out without
interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current
block-size transfer.
Rev. 3.00 Mar 17, 2006 page 364 of 926
REJ09B0283-0300
When the EDTCR value changes from 1 to 0, and transfer ends
When a repeat area overflow interrupt is requested, and transfer ends
When an NMI interrupt is generated, and transfer halts
A reset
Hardware standby mode
When 0 is written to the EDA bit, and transfer halts
EDTCR in normal transfer mode
EDTCR
EDTCR
EDTCR in block transfer mode
EDTCR
EDTCR
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and
23
23
23
23
Block
Block
size
size
16
16
1 to H'FFFFFF
Before update
Before update
15
15
0
1 to H'FFFF
Block Transfer Mode
0
0
0
0
0
Fixed
Fixed
–1
–1
23
23
23
23
Block
Block
size
size
16
16
0 to H'FFFFFE
After update
After update
15
15
0
0 to H'FFFE
0
0
0
0
0

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