D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 140

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 5 Interrupt Controller
5.3.1
INTCR selects the interrupt control mode, and the detected edge for NMI.
Bit
7, 6
5
4
3
2 to 0
5.3.2
IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt
Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7
in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding
interrupt. IPR should be read in word size.
Rev. 3.00 Mar 17, 2006 page 88 of 926
REJ09B0283-0300
Bit Name
—
INTM1
INTM0
NMIEG
—
Interrupt Control Register (INTCR)
Interrupt Priority Registers A to K (IPRA to IPRK)
Initial Value
All 0
0
0
0
All 0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
Interrupt Control Select Mode 1 and 0
These bits select either of two interrupt control
modes for the interrupt controller.
00: Interrupt control mode 0
01: Setting prohibited.
10: Interrupt control mode 2
11: Setting prohibited.
NMI Edge Select
Selects the input edge for the NMI pin.
0: Interrupt request generated at falling edge of
1: Interrupt request generated at rising edge of
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
NMI input
NMI input
Interrupts are controlled by I bit.
Interrupts are controlled by bits I2 to I0, and
IPR.