D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 771
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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15.7.2
Figure 15.22 shows the transfer data format in Smart Card interface mode.
Data transfer with the types of IC cards (direct convention and inverse convention) are performed
as described in the following.
One frame consists of 8-bit data plus a parity bit in asynchronous mode.
In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of
one bit) is left between the end of the parity bit and the start of the next frame.
If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
If an error signal is sampled during transmission, the same data is retransmitted automatically
after the elapse of 2 etu or longer.
When there is no parity error
When a parity error occurs
Data Format (Except for Block Transfer Mode)
Legend:
Ds
D0 to D7
Dp
DE
(Z)
Figure 15.23 Direct Convention (SDIR = SINV = O/E E E E = 0)
: Start bit
: Data bits
: Parity bit
: Error signal
Ds
Ds
Figure 15.22 Normal Smart Card Interface Data Format
Ds
A
D0
D0
D0 D1 D2 D3 D4 D5 D6 D7 Dp
Z
D1
D1
Z
Transmitting station output
Transmitting station output
D2
D2
A
Z
D3
D3
Section 15 Serial Communication Interface (SCI, IrDA)
Z
D4
D4
Z
D5
D5
A
Rev. 3.00 Mar 17, 2006 page 719 of 926
D6
D6
A
Z
D7
D7
Dp
Dp
(Z) State
Receiving station
output
DE
REJ09B0283-0300
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