D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 393
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.3.4
EDMDR controls EXDMAC operations.
Bit
15
Bit Name
EDA
EXDMA Mode Control Register (EDMDR)
Initial Value
0
R/W
R/(W)
Description
EXDMA Active
Enables or disables data transfer on the
corresponding channel. When this bit is set to
1, this indicates that an EXDMA operation is in
progress.
When auto request mode is specified (by bits
MDS1 and MDS0), transfer processing begins
when this bit is set to 1. With external requests,
transfer processing begins when a transfer
request is issued after this bit has been set to 1.
When this bit is cleared to 0 during an EXDMA
operation, transfer is halted. If this bit is cleared
to 0 during an EXDMA operation in block
transfer mode, transfer processing is continued
for the currently executing one-block transfer,
and the bit is cleared on completion of the
currently executing one-block transfer.
If an external source that ends (aborts) transfer
occurs, this bit is automatically cleared to 0 and
transfer is terminated. Do not change the
operating mode, transfer method, or other
parameters while this bit is set to 1.
0: Data transfer disabled on corresponding
[Clearing conditions]
1: Data transfer enabled on corresponding
Note: The value written in the EDA bit may not
be effective immediately.
channel
channel
When the specified number of transfers end
When operation is halted by a repeat area
overflow interrupt
When 0 is written to EDA while EDA = 1
(In block transfer mode, write is effective
after end of one-block transfer)
Reset, NMI interrupt, hardware standby
mode
Rev. 3.00 Mar 17, 2006 page 341 of 926
Section 8 EXDMA Controller
REJ09B0283-0300
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