D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 745

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.4.2
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched at the middle of each bit by sampling the data at
the rising edge of the 8th pulse of the basic clock as shown in figure 15.3. Thus the reception
margin in asynchronous mode is given by formula (1) below.
Where M: Reception Margin
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
Internal base
clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
M = (0.5 –
N: Ratio of bit rate to clock (N = 16)
D: Clock duty cycle (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
M = {0.5 – 1/(2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode
{
0
2N
8 clocks
Start bit
1
16)}
) – (L – 0.5) F –
16 clocks
100 [%] = 46.875%
7
Section 15 Serial Communication Interface (SCI, IrDA)
D – 0.5
N
15 0
(1 + F) × 100 [%]
Rev. 3.00 Mar 17, 2006 page 693 of 926
}
D0
7
REJ09B0283-0300
... Formula (1)
15 0
D1

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