D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 274

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 6 Bus Controller (BSC)
DQMU, DQML
Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone
(MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped
mode is entered, in which the bus controller and I/O port clocks are also stopped.
As the bus controller clock is also stopped in this mode, auto refreshing is not executed. If
synchronous DRAM is connected externally and DRAM data is to be retained in sleep mode, the
ACSE bit must be cleared to 0 in MSTPCR.
Software Standby: When a transition is made to normal software standby, the PLL command is
not output. If synchronous DRAM is connected and DRAM data is to be retained in software
standby, self-refreshing must be set.
Rev. 3.00 Mar 17, 2006 page 222 of 926
REJ09B0283-0300
Precharge-sel
Address bus
Figure 6.58 Example of Timing when Precharge Time after Self-Refreshing Is Extended
SDRAM
Data bus
CKE
RAS
CAS
WE
by 2 States (TPCS2 to TPCS0 = H'2, TPC1 = 0, TPC0 = 0, CAS Latency 2)
Software
standby
NOP
T
Rc2
T
Rp1
T
Rp2
Column address
PALL
T
p
Row address
Row address
Continuous synchronous DRAM space write
ACTV
T
r
T
NOP
c1
Column address
NOP
T
cl
NOP
T
c2