D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 68

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 1 Overview
Type
Bus control
Interrupt
signals
DMA controller
(DMAC)
Rev. 3.00 Mar 17, 2006 page 16 of 926
REJ09B0283-0300
Symbol
CAS
WE
WAIT
OE
(OE)
CKE
(CKE)
NMI
IRQ15 to
IRQ0
(IRQ15)
to (IRQ0)
DREQ1
DREQ0
(DREQ1)
(DREQ0)
FP-144G
(H8S/2678
Group)
—
—
85
112, 133
—
38
87, 86,
84 to 81,
61, 60,
130 to 127,
110 to 107
59 to 52,
112, 111,
4 to 2,
142 to 140
61, 60,
35, 34
Pin No.
112, 133
FP-144H
(H8S/2678R
Group)
104
105
85
112, 133
38
87, 86,
84 to 81,
61, 60,
130 to 127,
110 to 107
59 to 52,
112, 111,
4 to 2,
142 to 140
61, 60,
35, 34
I/O
Output Column address strobe signal for
Output Write enable signal for the
Input
Output Output enable signal for DRAM
Output Clock enable signal of the
Input
Input
Input
Function
the synchronous DRAM of the
synchronous DRAM interface.
synchronous DRAM of the
synchronous DRAM interface.
Requests insertion of a wait state in
the bus cycle when accessing
external 3-state address space.
interface space.
The output pins of OE and (OE) are
selected by the port function control
register 2 (PFCR2) of port 3.
synchronous DRAM interface
space.
The output pins of CKE and (CKE)
are selected by the port function
control register 2 (PFCR2) of port 3.
Nonmaskable interrupt request pin.
Fix high when not used.
These pins request a maskable
interrupt.
The input pins of DREQn and
(DREQn) are selected by the IRQ
pin select register (ITSR) of the
interrupt controller. (n = 0 to 15)
These signals request DMAC
activation.
The input pins of DREQn and
(DREQn) are selected by the IRQ
pin select register (ITSR) of the
interrupt controller. (n = 0 to 15)