D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 25

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

11.4 Operation .......................................................................................................................... 559
11.5 Interrupt Sources............................................................................................................... 583
11.6 DTC Activation................................................................................................................. 585
11.7 DMAC Activation............................................................................................................. 585
11.8 A/D Converter Activation ................................................................................................. 585
11.9 Operation Timing.............................................................................................................. 586
11.10 Usage Notes ...................................................................................................................... 594
Section 12 Programmable Pulse Generator (PPG)
12.1 Features ............................................................................................................................. 605
12.2 Input/Output Pins .............................................................................................................. 607
12.3 Register Descriptions ........................................................................................................ 607
11.3.7 Timer General Register (TGR) ............................................................................ 557
11.3.8 Timer Start Register (TSTR)................................................................................ 557
11.3.9 Timer Synchronous Register (TSYR) .................................................................. 558
11.4.1 Basic Functions.................................................................................................... 559
11.4.2 Synchronous Operation........................................................................................ 564
11.4.3 Buffer Operation .................................................................................................. 566
11.4.4 Cascaded Operation ............................................................................................. 570
11.4.5 PWM Modes ........................................................................................................ 572
11.4.6 Phase Counting Mode .......................................................................................... 577
11.9.1 Input/Output Timing ............................................................................................ 586
11.9.2 Interrupt Signal Timing........................................................................................ 590
11.10.1
11.10.2
11.10.3
11.10.4
11.10.5
11.10.6
11.10.7
11.10.8
11.10.9
11.10.10 Contention between Buffer Register Write and Input Capture ........................ 601
11.10.11 Contention between Overflow/Underflow and Counter Clearing.................... 602
11.10.12 Contention between TCNT Write and Overflow/Underflow........................... 603
11.10.13 Multiplexing of I/O Pins .................................................................................. 603
11.10.14 Interrupts and Module Stop Mode ................................................................... 603
12.3.1 Next Data Enable Registers H, L (NDERH, NDERL)......................................... 608
12.3.2 Output Data Registers H, L (PODRH, PODRL).................................................. 609
12.3.3 Next Data Registers H, L (NDRH, NDRL) ......................................................... 610
12.3.4 PPG Output Control Register (PCR).................................................................... 612
Module Stop Mode Setting .............................................................................. 594
Input Clock Restrictions................................................................................... 594
Caution on Cycle Setting ................................................................................. 595
Contention between TCNT Write and Clear Operations ................................. 595
Contention between TCNT Write and Increment Operations.......................... 596
Contention between TGR Write and Compare Match ..................................... 597
Contention between Buffer Register Write and Compare Match .................... 598
Contention between TGR Read and Input Capture.......................................... 599
Contention between TGR Write and Input Capture......................................... 600
Rev. 3.00 Mar 17, 2006 page xxiii of l
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