D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 47

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 6 Bus Controller (BSC)
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Table 6.7
Table 6.8
Table 6.9
Table 6.10
Table 6.11
Table 6.12
Table 6.13
Section 7 DMA Controller (DMAC)
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Table 7.10
Table 7.11
Table 7.12
Section 8 EXDMA Controller
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Section 9 Data Transfer Controller (DTC)
Table 9.1
Table 9.2
Table 9.3
Pin Configuration ................................................................................................... 123
Bus Specifications for Each Area (Basic Bus Interface) ........................................ 155
Data Buses Used and Valid Strobes ....................................................................... 160
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space............. 173
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing .... 174
DRAM Interface Pins............................................................................................. 175
Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous
DRAM Space ......................................................................................................... 198
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing .... 199
Synchronous DRAM Interface Pins ....................................................................... 201
Setting CAS Latency .............................................................................................. 204
Idle Cycles in Mixed Accesses to Normal Space and DRAM Continuous
Synchronous DRAM Space.................................................................................... 246
Pin States in Idle Cycle .......................................................................................... 249
Pin States in Bus Released State ............................................................................ 252
Pin Configuration ................................................................................................... 261
Short Address Mode and Full Address Mode (Channel 0)..................................... 262
DMAC Activation Sources .................................................................................... 286
DMAC Transfer Modes.......................................................................................... 288
Register Functions in Sequential Mode.................................................................. 290
Register Functions in Idle Mode ............................................................................ 293
Register Functions in Repeat Mode ....................................................................... 295
Register Functions in Single Address Mode .......................................................... 298
Register Functions in Normal Mode ...................................................................... 301
Register Functions in Block Transfer Mode........................................................... 304
DMAC Channel Priority Order .............................................................................. 325
Interrupt Sources and Priority Order ...................................................................... 329
Pin Configuration ................................................................................................... 337
EXDMAC Transfer Modes .................................................................................... 350
EXDMAC Channel Priority Order......................................................................... 366
Interrupt Sources and Priority Order ...................................................................... 395
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................ 409
Chain Transfer Conditions ..................................................................................... 412
Register Function in Normal Mode........................................................................ 412
Rev. 3.00 Mar 17, 2006 page xlv of l