D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 629
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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11.4.6
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 11.31 shows the correspondence between external clock pins and channels.
Table 11.31 Clock Input Pins in Phase Counting Mode
Example of Phase Counting Mode Setting Procedure: Figure 11.24 shows an example of the
phase counting mode setting procedure.
Channels
When channel 1 or 5 is set to phase counting mode
When channel 2 or 4 is set to phase counting mode
Phase Counting Mode
Figure 11.24 Example of Phase Counting Mode Setting Procedure
Select phase counting mode
<Phase counting mode>
Phase counting mode
Start count
[1]
[2]
[1]
[2]
Select phase counting mode with bits MD3 to
MD0 in TMDR.
Set the CST bit in TSTR to 1 to start the count
operation.
Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar 17, 2006 page 577 of 926
External Clock Pins
A-Phase
TCLKA
TCLKC
B-Phase
TCLKB
TCLKD
REJ09B0283-0300
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