D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 805

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

2. When A/D conversion for each channel is completed, the result is sequentially transferred to
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the
16.4.3
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (t
conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 indicates the A/D
conversion time.
As indicated in figure 16.2, the A/D conversion time (t
(t
conversion time therefore varies within the ranges indicated in tables 16.3.
In scan mode, the values given in tables 16.3 apply to the first conversion time. The values given
in tables 16.4 apply to the second and subsequent conversions. The conversion time must be
within the ranges indicated in the descriptions, A/D Conversion Characteristics in section 24,
Electrical Characteristics. Therefore the CKS and CKS1 bits (H8S/2678 Group) or CKS1 and
CKS0 bits (H8S/2678R Group) must be set to satisfy this condition.
SPL
the corresponding A/D data register to each channel.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
). The length of t
Input Sampling and A/D Conversion Time
D
varies depending on the timing of the write access to ADCSR. The total
D
) passes after the ADST bit is set to 1, then starts
CONV
Rev. 3.00 Mar 17, 2006 page 753 of 926
) includes t
D
and the input sampling time
Section 16 A/D Converter
REJ09B0283-0300