D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 458

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 9 Data Transfer Controller (DTC)
Bit
7
6
5
4
3
2
1
0
9.2.8
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit
7
6
5
4
3
2
1
0
Rev. 3.00 Mar 17, 2006 page 406 of 926
REJ09B0283-0300
Bit Name
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
Bit Name
SWDTE
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
DTC Vector Register (DTVECR)
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt
source to a DTC activation source.
[Clearing conditions]
These bits are not cleared when the DISEL bit is 0
and the specified number of transfers have not
ended
Description
DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be
written to this bit.
[Clearing conditions]
When the DISEL bit is 1 and data transfer has ended
or when the specified number of transfers have
ended, this bit will not be cleared.
DTC Software Activation Vectors 6 to 0
These bits specify a vector number for DTC software
activation.
The vector address is expressed as H'0400 + (vector
number
DTVEC0 = H'10, the vector address is H'0420. When
the bit SWDTE is 0, these bits can be written.
When the DISEL bit is 1 and the data transfer has
ended
When the specified number of transfers have
ended
When the DISEL bit is 0 and the specified
number of transfers have not ended
When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the CPU.
2). For example, when DTVEC6 to