D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 22

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

9.6
9.7
9.8
Section 10 I/O Ports
10.1 Port 1................................................................................................................................. 432
10.2 Port 2................................................................................................................................. 443
10.3 Port 3................................................................................................................................. 454
10.4 Port 4................................................................................................................................. 461
10.5 Port 5................................................................................................................................. 462
Rev. 3.00 Mar 17, 2006 page xx of l
9.5.3
9.5.4
9.5.5
9.5.6
9.5.7
Procedures for Using DTC................................................................................................ 420
9.6.1
9.6.2
Examples of Use of the DTC ............................................................................................ 421
9.7.1
9.7.2
9.7.3
9.7.4
Usage Notes ...................................................................................................................... 426
9.8.1
9.8.2
9.8.3
10.1.1 Port 1 Data Direction Register (P1DDR)............................................................. 432
10.1.2 Port 1 Data Register (P1DR)................................................................................ 433
10.1.3 Port 1 Register (PORT1)...................................................................................... 433
10.1.4 Pin Functions ....................................................................................................... 434
10.2.1 Port 2 Data Direction Register (P2DDR)............................................................. 443
10.2.2 Port 2 Data Register (P2DR)................................................................................ 444
10.2.3 Port 2 Register (PORT2)...................................................................................... 444
10.2.4 Pin Functions ....................................................................................................... 445
10.3.1 Port 3 Data Direction Register (P3DDR)............................................................. 454
10.3.2 Port 3 Data Register (P3DR)................................................................................ 455
10.3.3 Port 3 Register (PORT3)...................................................................................... 455
10.3.4 Port 3 Open Drain Control Register (P3ODR)..................................................... 456
10.3.5 Port Function Control Register 2 (PFCR2) .......................................................... 457
10.3.6 Pin Functions ....................................................................................................... 458
10.4.1 Port 4 Register (PORT4)...................................................................................... 461
10.4.2 Pin Functions ....................................................................................................... 461
10.5.1 Port 5 Data Direction Register (P5DDR)............................................................. 463
Block Transfer Mode ........................................................................................... 414
Chain Transfer ..................................................................................................... 415
Interrupt Sources.................................................................................................. 416
Operation Timing................................................................................................. 417
Number of DTC Execution States........................................................................ 418
Activation by Interrupt......................................................................................... 420
Activation by Software ........................................................................................ 420
Normal Mode....................................................................................................... 421
Chain Transfer ..................................................................................................... 422
Chain Transfer when Counter = 0........................................................................ 423
Software Activation ............................................................................................. 425
Module Stop Mode Setting .................................................................................. 426
On-Chip RAM ..................................................................................................... 426
DTCE Bit Setting................................................................................................. 426
............................................................................................................ 427