D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 245

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of
standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP
instruction is executed to enter software standby mode, the CAS and RAS signals are output and
DRAM enters self-refresh mode, as shown in figure 6.39.
When software standby mode is exited, the SLFRF bit is cleared to 0 and self-refresh mode is
exited automatically. If a CBR refresh request occurs when making a transition to software
standby mode, CBR refreshing is executed, then self-refresh mode is entered.
When using self-refresh mode, the OPE bit must not be cleared to 0 in the SBYCR register.
A23 to A0
CS
AS
RD
HWR (WE)
RAS
CAS
Figure 6.38 Example of CBR Refresh Timing (CBRM = 1)
Normal space access request
Refresh period
Rev. 3.00 Mar 17, 2006 page 193 of 926
Section 6 Bus Controller (BSC)
REJ09B0283-0300

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