D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 292

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 6 Bus Controller (BSC)
Idle Cycle in Case of Normal Space Access after DRAM Space Access:
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is
disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to
1. The conditions and number of states of the idle cycle to be inserted are in accordance with the
settings of bits ICIS1, ICIS0, and IDLC in BCR are valid. Figures 6.76 and 6.77 show examples of
idle cycle operation when the DRMI bit is set to 1.
Rev. 3.00 Mar 17, 2006 page 240 of 926
REJ09B0283-0300
Precharge-sel
DQMU, DQML
Address bus
Normal space access after DRAM space read access
HWR, LWR
Data bus
CKE
CAS
RAS
WE
RD
Figure 6.75 Example of Idle Cycle Operation in RAS Down Mode
PALL ACTV READ
address
Column
T
p
(Write after Read) (IDLC = 0, CAS Latency 2)
Continuous synchronous
DRAM space read
address
address
Row
Row
T
r
T
Column address 1
c1
T
cl
High
High
T
c2
External space read
T
External address
External address
1
NOP
T
2
T
3
Idle cycle
T
Continuous synchronous
DRAM space write
i
Column address 2
T
c1
WRIT
T
Cl
NOP
T
c2