D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 789

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
15.10.7 Operation in Case of Mode Transition
Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin
states in module stop mode or software standby mode depend on the port settings, and become
high-level output after the relevant mode is cleared. If a transition is made during transmission,
the data being transmitted will be undefined.
When transmitting without changing the transmit mode after the relevant mode is cleared,
transmission can be started by setting TE to 1 again, and performing the following sequence:
SSR read
clearing the relevant mode, the procedure must be started again from initialization.
Figure 15.36 shows a sample flowchart for mode transition during transmission. Port pin states
during mode transition are shown in figures 15.37 and 15.38.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a
transition from transmission by DTC transfer to module stop mode or software standby mode
transition. To perform transmission with the DTC after the relevant mode is cleared, setting TE
and TIE to 1 will set the TXI flag and start DTC transmission.
Reception
Receive operation should be stopped (by clearing RE to 0) before making a module stop mode
or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made
during reception, the data being received will be invalid.
To continue receiving without changing the reception mode after the relevant mode is cleared,
set RE to 1 before starting reception. To receive with a different receive mode, the procedure
must be started again from initialization.
SCK
TDRE
Serial data
Note: When operating on an external clock, set t > 4 clocks.
Figure 15.35 Example of Synchronous Transmission Using DTC
TDR write
t
LSB
D0
TDRE clearance. To transmit with a different transmit mode after
D1
D2
Section 15 Serial Communication Interface (SCI, IrDA)
D3
Rev. 3.00 Mar 17, 2006 page 737 of 926
D4
D5
D6
REJ09B0283-0300
D7

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