D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 203
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 203 of 981
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Bit
5
4
3
2
1
0
Bit Name
RLW1
RLW0
SLFRF
TPCS2
TPCS1
TPCS0
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Refresh Cycle Wait Control
These bits select the number of wait states to
be inserted in a DRAM interface CAS-before-
RAS refresh cycle/synchronous DRAM
interface auto-refresh cycle. This setting applies
to all areas designated as DRAM/continuous
synchronous DRAM space.
00: No wait state inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
Self-Refresh Enable
If this bit is set to 1, DRAM/synchronous DRAM
self-refresh mode is selected when a transition
is made to the software standby state. This bit
is valid when the RFSHE bit is set to 1,
enabling refresh operations. It is cleared after
recovery from software standby mode.
0: Self-refreshing is disabled
1: Self-refreshing is enabled
Self-Refresh Precharge Cycle Control
These bits select the number of states in the
precharge cycle immediately after self-
refreshing.
The number of states in the precharge cycle
immediately after self-refreshing are added to
the number of states set by bits TPC1 and
TPC0 in DRACCR.
000: [TPC set value] states
001: [TPC set value + 1] states
010: [TPC set value + 2] states
011: [TPC set value + 3] states
100: [TPC set value + 4] states
101: [TPC set value + 5] states
110: [TPC set value + 6] states
111: [TPC set value + 7] states
Rev. 3.00 Mar 17, 2006 page 151 of 926
Section 6 Bus Controller (BSC)
REJ09B0283-0300
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