D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 209

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 6 Bus Controller (BSC)
If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64-
Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are
used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The
OE pin is used as the CKE signal.
Area 6: In externally expanded mode, all of area 6 is external space.
When area 6 external space is accessed, the CS6 signal can be output.
Only the basic bus interface can be used for area 6.
Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode,
the space excluding the on-chip RAM and internal I/O registers is external address space. The on-
chip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when
the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external address space.
When area 7 external address space is accessed, the CS7 signal can be output.
Only the basic bus interface can be used for the area 7 memory interface.
6.4.4
Chip Select Signals
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7
signals output timing.
Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit
for the port corresponding to the CS0 to CS7 pins.
In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a
reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits
should be set to 1 when outputting signals CS1 to CS7.
In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state
after a reset and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to
CS7.
When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals.
When areas 2 to 5 are designated as continuous synchronous DRAM space in the H8S/2678R
Group, outputs CS2 to CS5 are used as RAS, CAS, WE, and CLK signals.
Rev. 3.00 Mar 17, 2006 page 157 of 926
REJ09B0283-0300