D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 305

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

6.11.3
Figure 6.84 shows the timing for transition to the bus released state.
Figure 6.85 shows the timing for transition to the bus released state with the synchronous DRAM
interface.
Address bus
HWR, LWR
Data bus
BREQO
BREQ
BACK
RD
AS
[1] Low level of BREQ signal is sampled at rise of ø.
[2] Bus control signal returns to be high at end of external space access cycle.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access or refresh request of internal bus master during external
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.
Transition Timing
At least one state from sampling of BREQ signal.
bus release while BREQOE bit is set to 1, BREQO signal goes low.
External space
access cycle
T
Figure 6.84 Bus Released State Transition Timing
1
[1]
T
2
[2]
[3]
[4]
[5]
External bus released state
Rev. 3.00 Mar 17, 2006 page 253 of 926
High-Z
High-Z
High-Z
High-Z
High-Z
Section 6 Bus Controller (BSC)
[6]
REJ09B0283-0300
[7]
[8]
CPU
cycle