D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 849

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address
2. Verify data is read in 16-bit (W) units.
3. The reprogram data is given by the operation of the following tables (comparison
4. A 128-byte areas for storing program data, reprogram data, and additional
5. A write pulse of (z1) or (z2) µs should be applied according to the progress of the
6. For the values of x, y, z1, z2, z3, , , , , , , and N, see section 24.6, Flash
written to must be H'00 or H'80. A 128-byte data transfer must be performed even
if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra
addresses.
between stored data in the program data area and verify data). Programming is
executed for the bits of reprogram data 0 in the next reprogram loop. Even bits for
which programming has been completed will be subjected to additional
programming if they fail the subsequent verify operation.
program data must be provided in the RAM. The contents of the reprogram and
additional program data are modified as programming proceeds.
programming operation. See note 7 for the pulse widths. When writing of
additional-programming data is executed, a (z3) s write pulse should be applied.
Reprogram data X' means reprogram data when the write pulse is applied.
Memory Characteristics.
Program Data Operation Chart
Original Data
Note 7: Write Pulse Width
Note: Use a z3 µs write pulse for additional programming.
(D)
Number of Writes (n)
Reprogram data storage
Additional program data
storage area (128 bytes)
0
1
Write pulse application subroutine
Wait (z1) ms or (z2) ms or (z3) ms
Program data storage
area (128 bytes)
area (128 bytes)
Clear PSU bit in FLMCR1
Set PSU bit in FLMCR1
Write pulse application
Clear P bit in FLMCR1
1000
Set P bit in FLMCR1
998
999
10
11
12
13
RAM
1
2
3
4
5
6
7
8
9
Verify Data
.
.
.
Disable WDT
Enable WDT
Wait ( ) ms
Wait ( ) ms
Wait (y) s
(V)
End sub
0
1
0
1
Reprogram Data
Write Time (z) ms
Figure 19.10 Program/Program-Verify Flowchart
(X)
1
0
1
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
.
.
.
*6
*5 *6
*6
*6
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Increment address
Comments
Store 128-byte program data in program
NG
data area consecutively to flash memory
additional program data area in RAM to
Write 128-byte data in RAM reprogram
Transfer reprogram data to reprogram
Additional program data computation
H'FF dummy write to verify address
Transfer additional program data to
Sequentially write 128-byte data in
data area and reprogram data area
Additional Program Data Operation Chart
Reprogram Data
Reprogram data computation
additional program data area
Clear SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set SWE bit in FLMCR1
(additional programming)
Write pulse application
Set PV bit in FLMCR1
Start of programming
Write pulse application
End of programming
Write data = verify
Read verify data
(X')
(z1) s or (z2) s
data verification
0
1
Section 19 Flash Memory (F-ZTAT Version)
flash memory
Wait (x) ms
Wait ( ) ms
Wait ( ) ms
completed?
Wait ( ) ms
Wait ( ) ms
data area
128-byte
6
6
m = 0?
m = 0
(z3) µs
n = 1
data?
Start
Rev. 3.00 Mar 17, 2006 page 797 of 926
n ?
n ?
OK
OK
OK
OK
OK
Verify Data
Sub-routine-call
Sub-routine-call
(V)
0
1
0
1
NG
NG
NG
NG
Additional Program
*6
Data (Y)
*6
*4
*1
See note 7 for pulse width
*6
*2
*3
*4
*6
*1
*6
*4
0
1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
m = 1
Clear SWE bit in FLMCR1
Programming failure
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
Wait ( ) ms
n
(N)?
OK
REJ09B0283-0300
*6
Comments
NG
n
n + 1
*6