D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 295
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 295 of 981
- Download datasheet (6Mb)
Section 6 Bus Controller (BSC)
DRAM space read
External space read
DRAM space read
T
T
T
T
T
T
T
T
T
T
p
r
c1
c2
i
1
2
3
c1
c2
Address bus
RD
HWR, LWR
RAS
UCAS, LCAS
Data bus
Idle cycle
Figure 6.78 Example of Idle Cycle Operation after DRAM Write Access
(IDLC = 0, ICIS1 = 0, RAST = 0, CAST = 0)
Idle Cycle in Case of Normal Space Access After Continuous Synchronous DRAM Space
Access:
Note: In the H8S/2678 Group, the synchronous DRAM interface is not supported.
Normal space access after a continuous synchronous DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous
DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM
space read access can be enabled by setting the DRMI bit to 1. The conditions and number of
states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and
IDLC in RCR. Figure 6.79 shows an example of idle cycle operation when the DRMI bit is set to
1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous
DRAM space read access even if bits ICIS1 and ICIS0 are set to 1.
Rev. 3.00 Mar 17, 2006 page 243 of 926
REJ09B0283-0300
Related parts for D12674RVFQ33D
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CCD Vertical Clock Driver
Manufacturer:
Sony Corporation
Datasheet:
Part Number:
Description:
KIT STARTER FOR M16C/29
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/2D
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
R0K33062P STARTER KIT
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/23 E8A
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C/25
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER H8S2456 SHARPE DSPLY
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C38C
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8C35C
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R8CL3AC+LCD APPS
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR RX610
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR R32C/118
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT DEV RSK-R8C/26-29
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR SH7124
Manufacturer:
Renesas Electronics America
Datasheet:
Part Number:
Description:
KIT STARTER FOR H8SX/1622
Manufacturer:
Renesas Electronics America
Datasheet: