D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 410
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 410 of 981
- Download datasheet (6Mb)
Section 8 EXDMA Controller
Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the
block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify
the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256
can be specified. During transfer of a block, transfer requests for other higher-priority channels are
held pending. When transfer of one block is completed, the bus is released in the next cycle.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus mastership during block transfer.
Address register values are updated in the same way as in normal mode. There is no function for
restoring the initial address register values after each block transfer.
The ETEND signal is output for each block transfer in the DMA transfer cycle in which the block
ends. The EDRAK signal is output once for one transfer request (for transfer of one block).
Rev. 3.00 Mar 17, 2006 page 358 of 926
REJ09B0283-0300
Bus cycle
ETEND
Transfer conditions:
Dual address mode, auto request mode
EDREQ
EDRAK
Bus cycle
EDACK
Transfer conditions:
Single address mode, external request mode
Figure 8.7 Examples of Timing in Normal Transfer Mode
Read
transfer cycle
EXDMA
Write
EXDMA
Read
Last EXDMA
transfer cycle
EXDMA
Write
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