D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 580

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 11 16-Bit Timer Pulse Unit (TPU)
11.3.1
The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR
registers, one for each channel. TCR register settings should be made only when TCNT operation
is stopped.
Bit
7
6
5
4
3
2
1
0
Rev. 3.00 Mar 17, 2006 page 528 of 926
REJ09B0283-0300
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Counter Clear 2 to 0
These bits select the TCNT counter clearing source.
See tables 11.3 and 11.4 for details.
Clock Edge 1 and 0
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. /4 both edges = /2
rising edge). If phase counting mode is used on
channels 1, 2, 4, and 5, this setting is ignored and
the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is
is /1, or when overflow/underflow of another
channel is selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Legend: x: Don’t care
Time Prescaler 2 to 0
These bits select the TCNT counter clock. The clock
source can be selected independently for each
channel. See tables 11.5 to 11.10 for details.
/4 or slower. This setting is ignored if the input clock