D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 407

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
8.4.3
Auto Request Mode: In auto request mode, transfer request signals are automatically generated
within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in
transfer between two memories, or between a peripheral module that is not capable of generating
transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to
1 in EDMDR.
In auto request mode, either cycle steal mode or burst mode can be selected as the bus mode.
Block transfer mode cannot be used.
External Request Mode: In external request mode, transfer is started by a transfer request signal
(EDREQ) from a device external to this LSI. DMA transfer is started when EDREQ is input while
DMA transfer is enabled (EDA = 1).
The transfer request source need not be the data transfer source or data transfer destination.
The transfer request signal is accepted via the EDREQ pin. Either falling edge sensing or low level
sensing can be selected for the EDREQ pin by means of the EDREQS bit in EDMDR (low level
sensing when EDREQS = 0, falling edge sensing when EDREQS = 1).
Setting the EDRAKE bit to 1 in EDMDR enables a signal confirming transfer request acceptance
to be output from the EDRAK pin. The EDRAK signal is output when acceptance and transfer
processing has been started in response to a single external request. The EDRAK signal enables
the external device to determine the timing of EDREQ signal negation, and makes it possible to
provide handshaking between the transfer request source and the EXDMAC.
In external request mode, block transfer mode can be used instead of burst mode. Block transfer
mode allows continuous execution (burst operation) of the specified number of transfers (the block
size) in response to a single transfer request. In block transfer mode, the EDRAK signal is output
only once for a one-block transfer, since the transfer request via the EDREQ pin is for a block
unit.
8.4.4
There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto
request, either cycle steal mode or burst mode can be selected. When the activation source is an
external request, cycle steal mode is used.
Cycle Steal Mode: In cycle steal mode, the EXDMAC releases the bus at the end of each transfer
of a transfer unit (byte, word, or block). If there is a subsequent transfer request, the EXDMAC
DMA Transfer Requests
Bus Modes
Rev. 3.00 Mar 17, 2006 page 355 of 926
Section 8 EXDMA Controller
REJ09B0283-0300

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