D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 663
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit
7
to
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
to
0
Bit Name
—
NDR11
NDR10
NDR9
NDR8
Bit Name
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
Bit Name
NDR7
NDR6
NDR5
NDR4
—
Initial Value
All 1
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
All 1
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Reserved
These bits are always read as 1 and cannot be
modified.
Next Data Register 11 to 8
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
Next Data Register 7 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Next Data Register 7 to 4
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
These bits are always read as 1 and cannot be
modified.
Description
Description
Description
Section 12 Programmable Pulse Generator (PPG)
Rev. 3.00 Mar 17, 2006 page 611 of 926
REJ09B0283-0300
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