D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 874

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 22 Power-Down Modes
22.1
The registers relating to the power-down mode are shown below. For details on the system clock
control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR).
22.1.1
SBYCR performs software standby mode control.
Bit
7
6
Rev. 3.00 Mar 17, 2006 page 822 of 926
REJ09B0283-0300
System clock control register (SCKCR)
Standby control register (SBYCR)
Module stop control register H (MSTPCRH)
Module stop control register L (MSTPCRL)
Bit Name
SSBY
OPE
Register Descriptions
Standby Control Register (SBYCR)
Initial Value
0
1
R/W
R/W
R/W
Description
Software Standby
This bit specifies the transition mode after
executing the SLEEP instruction
0: Shifts to sleep mode after the SLEEP instruction
1: Shifts to software standby mode after the
This bit does not change when clearing the
software standby mode by using external interrupts
and shifting to normal operation. This bit should be
written 0 when clearing.
Output Port Enable
Specifies whether the output of the address bus
and bus control signals (CS0 to CS7, AS, RD,
HWR, LWR, UCAS, LCAS) is retained or set to the
high-impedance state in software standby mode.
0: In software standby mode, address bus and bus
1: In software standby mode, address bus and bus
is executed
SLEEP instruction is executed
control signals are high-impedance
control signals retain output state