D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 425

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

EDREQ pin sampling is performed in each cycle starting at the next rise of after the end of the
EDMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the EDREQ pin while acceptance via the EDREQ pin is possible,
the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC,
the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ
pin high level sampling is completed by the end of the DMA write cycle, acceptance resumes after
the end of the write cycle, and EDREQ pin low level sampling is performed again; this sequence
of operations is repeated until the end of the transfer.
[1]
[2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
[3], [6] DMA cycle start; EDREQ pin high level sampling is started at rise of .
[4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of dead cycle.
EDREQ
Address bus
DMA control
Channel
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of , and request is held.
(As in [1], EDREQ pin low level is sampled at rise of , and request is held.)
Idle
Figure 8.19 Example of Block Transfer Mode Transfer Activated
[1]
Minimum 3 cycles
Bus release
Request
[2]
Read
Request clearance period
[3]
Transfer source
DMA read
by EDREQ
One block transfer
Write
EDREQ Pin Falling Edge
EDREQ
EDREQ
DMA write
destination
Transfer
Acceptance
resumed
Idle
[4]
Minimum 3 cycles
Request
Bus release
Rev. 3.00 Mar 17, 2006 page 373 of 926
[5]
Request clearance period
Read
[6]
Transfer source
DMA read
Section 8 EXDMA Controller
One block transfer
Write
DMA write Bus release
destination
REJ09B0283-0300
Transfer
Acceptance
resumed
Idle
[7]