D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 766

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 15 Serial Communication Interface (SCI, IrDA)
15.6.4
Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart
for serial data reception.
Rev. 3.00 Mar 17, 2006 page 714 of 926
REJ09B0283-0300
Serial
clock
Serial
data
RDRF
ORER
or output, starts receiving data, and stores the received data in RSR.
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
RXI interrupt request
generated
Serial Data Reception (Clocked Synchronous Mode)
Figure 15.18 Example of SCI Operation in Reception
Bit 7
RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
Bit 0
1 frame
Bit 7
Bit 0
RXI interrupt request
generated
Bit 1
ERI interrupt request
generated by overrun
error
Bit 6
Bit 7