D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 129

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Notes: 1. Lower 16 bits of the address.
4.3
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 14,
Watchdog Timer.
The interrupt control mode is 0 immediately after reset.
4.3.1
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
2. The reset exception handling vector address is read and transferred to the PC, and program
Figures 4.1 and 4.2 show examples of the reset sequence.
Exception Source
External interrupt IRQ13
Internal interrupt *
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
execution starts from the address indicated by the PC.
2. Not available in this LSI.
3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Reset
Reset exception handling
Vector Table.
3
IRQ14
IRQ15
Vector Number
29
30
31
32
99

Normal Mode *
H'003A to H'003B
H'003C to H'003D
H'003E to H'003F
H'0040 to H'0041
H'00C6 to H'00C7
Rev. 3.00 Mar 17, 2006 page 77 of 926
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Vector Address *
Section 4 Exception Handling
2
Advanced Mode
H'0074 to H'0077
H'0078 to H'007B
H'007C to H'007F
H'0080 to H'0083
H'018C to H'018F
REJ09B0283-0300
1
