D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 671
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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12.4.4
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
Figure 12.6 illustrates the non-overlapping pulse output operation.
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A.
The NDR contents should not be altered during the interval from compare match B to compare
match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next
data must be written before the next compare match B occurs.
Figure 12.7 shows the timing of this operation.
If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained
without imposing a load on the CPU.
NDR bits are always transferred to PODR bits at compare match A.
At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Pulse
output
pin
Non-Overlapping Pulse Output
DDR
Figure 12.6 Non-Overlapping Pulse Output
Normal output/inverted output
Q
NDER
Q
PODR
C
Section 12 Programmable Pulse Generator (PPG)
D
Rev. 3.00 Mar 17, 2006 page 619 of 926
Q
NDR
Compare match A
Compare match B
D
Internal data bus
REJ09B0283-0300
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