D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 449

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Figure 8.46 Example of Procedure for Restarting Transfer on Channel in which Transfer
[1] Write set values to the registers (transfer counter, address registers, etc.).
[2] Write 1 to the EDA bit in EDMDR to restart EXDMA operation. When 1 is written to the
[3] The interrupt handling routine is ended with an RTE instruction, etc.
[4] Clear the IRF bit to 0 in EDMDR by first reading 1 from it, then writing 0.
[5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt
[6] Write set values to the registers (transfer counter, address registers, etc.).
[7] Write 1 to the EDA bit in EDMDR to restart EXDMA operation.
EDA bit, the IRF bit in EDMDR is automatically cleared to 0 and the interrupt source is
cleared.
masking is cleared.
(RTE instruction execution)
exception handling routine
End of interrupt handling
Change register settings
End of transfer restart
Transfer end interrupt
Transfer continuation
Write 1 to EDA bit
processing
processing
routine
End Interrupt Occurred
[1]
[2]
[3]
of interrupt handling routine
Rev. 3.00 Mar 17, 2006 page 397 of 926
Transfer restart after end
End of interrupt handling
Change register settings
End of transfer restart
Write 1 to EDA bit
Clear IRF bit to 0
processing
routine
Section 8 EXDMA Controller
REJ09B0283-0300
[4]
[5]
[6]
[7]

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