D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 384

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 7 DMA Controller (DMAC)
7.7.4
If the last transfer cycle is for an internal address, note that even if low-level output at the TEND
pin has been set, a low level may not be output at the TEND pin under the following external bus
conditions since the last transfer cycle (internal bus cycle) and the external bus cycle are executed
in parallel.
1. EXDMAC cycle
2. Write cycle with write buffer mode enabled
3. DMAC single address cycle for a different channel with write buffer mode enabled
4. Bus release cycle
5. CBR refresh cycle
Figure 7.41 shows an example in which a low level is not output from the TEND pin in case 2
above.
If the last transfer cycle is an external address cycle, a low level is output at the TEND pin in
synchronization with the bus cycle.
However, if the last transfer cycle and a CBR refresh occur simultaneously, note that although the
CBR refresh and the last transfer cycle may be executed consecutively, TEND may also go low in
this case for the refresh cycle.
Rev. 3.00 Mar 17, 2006 page 332 of 926
REJ09B0283-0300
Write data buffer function and DMAC register setting
If the setting of a register that controls external accesses is changed during execution of an
external access by means of the write data buffer function, the external access may not be
performed normally. Registers that control external accesses should only be manipulated when
external reads, etc., are used with DMAC operation disabled, and the operation is not
performed in parallel with external access.
Write data buffer function and DMAC operation timing
The DMAC can start its next operation during external access using the write data buffer
function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are
different from the case in which the write data buffer function is disabled. Also, internal bus
cycles maybe hidden, and not visible.
TEND
TEND Output
TEND
TEND