D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 455

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

9.2.1
MRA selects the DTC operating mode.
Bit
7
6
5
4
3
2
1
Bit Name
SM1
SM0
DM1
DM0
MD1
MD0
DTS
DTC Mode Register A (MRA)
Initial Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
R/W
—
—
—
—
—
—
—
Description
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0x: SAR is fixed
10: SAR is incremented after a transfer
11: SAR is decremented after a transfer
Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0x: DAR is fixed
10: DAR is incremented after a transfer
11: DAR is decremented after a transfer
DTC Mode
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area, in
repeat mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
(by +1 when Sz = 0; by +2 when Sz = 1)
(by –1 when Sz = 0; by –2 when Sz = 1)
(by +1 when Sz = 0; by +2 when Sz = 1)
(by –1 when Sz = 0; by –2 when Sz = 1)
Section 9 Data Transfer Controller (DTC)
Rev. 3.00 Mar 17, 2006 page 403 of 926
REJ09B0283-0300