D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 869

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

2. A value is set in bits STS3 to STS0 to give the specified transition time.
3. The target value is set in bits STC1 and STC0, and a transition is made to software standby
4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
5. Software standby mode is cleared, and a transition time is secured in accordance with the
6. After the set transition time has elapsed, this LSI resumes operation using the target
When STCS = 1, this LSI operates using the new multiplication factor immediately after bits
STC1 and STC0 are rewritten.
21.4
The frequency divider divides the PLL output clock to generate a 1/2, 1/4, 1/8, 1/16, or 1/32 clock.
21.5
21.5.1
1. The following points should be noted since the frequency of changes according to the setting
2. All the on-chip peripheral modules operate on the . Therefore, note that the time processing
3. Note that the frequency of will be changed when setting SCKCR or PLLCR while executing
21.5.2
Since various characteristics related to the resonator are closely linked to the user’s board design,
thorough evaluation is necessary on the user’s part, using the oscillator connection examples
shown in this section as a guide. As the parameters for the oscillation circuit will depend on the
floating capacitance of the resonator and the user board, the parameters should be determined in
mode.
setting in STS3 to STS0.
multiplication factor.
of SCKCR and PLLCR.
Select the clock division ratio that is within the operation guaranteed range of clock cycle time
tcyc shown in the AC timing of Electrical Characteristics. In other words, the range of must
be specified from 8 MHz (min) to 33 MHz (max); outside of this range must be prevented.
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio. See the description, Setting Oscillation Stabilization Time after Clearing Software
Standby Mode, in section 22.2.3, Software Standby Mode, for details.
the external bus cycle with the write-data-buffer function or the EXDMAC.
Frequeny Divider
Usage Notes
Notes on Clock Pulse Generator
Notes on Resonator
Rev. 3.00 Mar 17, 2006 page 817 of 926
Section 21 Clock Pulse Generator
REJ09B0283-0300