D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 150

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Interrupt Controller
5.3.5
ISR is an IRQ15 to IRQ0 interrupt request flag register.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Note:
5.3.6
ITSR selects input pins IRQ15 to IRQ0.
Bit
15
14
Rev. 3.00 Mar 17, 2006 page 98 of 926
REJ09B0283-0300
* Only 0 can be written, to clear the flag.
Bit Name
IRQ15F
IRQ14F
IRQ13F
IRQ12F
IRQ11F
IRQ10F
IRQ9F
IRQ8F
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
Bit Name
ITS15
ITS14
IRQ Status Register (ISR)
IRQ Pin Select Register (ITSR)
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Initial Value
0
0
R/W
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/(W) *
R/W
R/W
R/W
Description
[Setting condition]
When the interrupt source selected by ISCR
occurs
[Clearing conditions]
Description
Selects IRQ15 input pin.
0: PF2
1: P27
Selects IRQ14 input pin.
0: PF1
1: P26
Cleared by reading IRQnF flag when IRQnF
= 1, then writing 0 to IRQnF flag
When interrupt exception handling is
executed when low-level detection is set
and IRQn input is high
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
(n=15 to 0)

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