D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 40

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Figure 11.22 Example of PWM Mode Operation (2)................................................................ 575
Figure 11.23 Example of PWM Mode Operation (3)................................................................ 576
Figure 11.24 Example of Phase Counting Mode Setting Procedure ......................................... 577
Figure 11.25 Example of Phase Counting Mode 1 Operation................................................... 578
Figure 11.26 Example of Phase Counting Mode 2 Operation................................................... 579
Figure 11.27 Example of Phase Counting Mode 3 Operation................................................... 580
Figure 11.28 Example of Phase Counting Mode 4 Operation................................................... 581
Figure 11.29 Phase Counting Mode Application Example ....................................................... 582
Figure 11.30 Count Timing in Internal Clock Operation .......................................................... 586
Figure 11.31 Count Timing in External Clock Operation ......................................................... 586
Figure 11.32 Output Compare Output Timing .......................................................................... 587
Figure 11.33 Input Capture Input Signal Timing ...................................................................... 587
Figure 11.34 Counter Clear Timing (Compare Match)............................................................. 588
Figure 11.35 Counter Clear Timing (Input Capture)................................................................. 588
Figure 11.36 Buffer Operation Timing (Compare Match) ........................................................ 589
Figure 11.37 Buffer Operation Timing (Input Capture)............................................................ 589
Figure 11.38 TGI Interrupt Timing (Compare Match).............................................................. 590
Figure 11.39 TGI Interrupt Timing (Input Capture).................................................................. 591
Figure 11.40 TCIV Interrupt Setting Timing ............................................................................ 592
Figure 11.41 TCIU Interrupt Setting Timing ............................................................................ 592
Figure 11.42 Timing for Status Flag Clearing by CPU............................................................. 593
Figure 11.43 Timing for Status Flag Clearing by DTC/DMAC Activation .............................. 593
Figure 11.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... 594
Figure 11.45 Contention between TCNT Write and Clear Operations ..................................... 595
Figure 11.46 Contention between TCNT Write and Increment Operations.............................. 596
Figure 11.47 Contention between TGR Write and Compare Match ......................................... 597
Figure 11.48 Contention between Buffer Register Write and Compare Match ........................ 598
Figure 11.49 Contention between TGR Read and Input Capture.............................................. 599
Figure 11.50 Contention between TGR Write and Input Capture............................................. 600
Figure 11.51 Contention between Buffer Register Write and Input Capture ............................ 601
Figure 11.52 Contention between Overflow and Counter Clearing .......................................... 602
Figure 11.53 Contention between TCNT Write and Overflow ................................................. 603
Section 12 Programmable Pulse Generator (PPG)
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Rev. 3.00 Mar 17, 2006 page xxxviii of l
Block Diagram of PPG ........................................................................................ 606
Overview Diagram of PPG .................................................................................. 615
Timing of Transfer and Output of NDR Contents (Example).............................. 616
Setup Procedure for Normal Pulse Output (Example) ......................................... 617
Normal Pulse Output Example (Five-Phase Pulse Output).................................. 618
Non-Overlapping Pulse Output............................................................................ 619
Non-Overlapping Operation and NDR Write Timing.......................................... 620