D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 626

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 11 16-Bit Timer Pulse Unit (TPU)
Example of PWM Mode Setting Procedure: Figure 11.20 shows an example of the PWM mode
setting procedure.
Examples of PWM Mode Operation: Figure 11.21 shows an example of PWM mode 1
operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as
the duty cycle.
Rev. 3.00 Mar 17, 2006 page 574 of 926
REJ09B0283-0300
Select counter clearing source
Select waveform output level
Select counter clock
Set PWM mode
<PWM mode>
PWM mode
Start count
Set TGR
Figure 11.20 Example of PWM Mode Setting Procedure
[1]
[2]
[3]
[4]
[5]
[6]
[1] Select the counter clock with bits TPSC2 to
[2] Use bits CCLR2 to CCLR0 in TCR to select the
[3] Use TIOR to designate the TGR as an output
[4] Set the cycle in the TGR selected in [2], and
[5] Select the PWM mode with bits MD3 to MD0 in
[6] Set the CST bit in TSTR to 1 to start the count
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
TGR to be used as the TCNT clearing source.
compare register, and select the initial value and
output value.
set the duty in the other TGRs.
TMDR.
operation.