D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 182

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
Bit
10
9
8
Note:
Legend: x: Don’t care.
Rev. 3.00 Mar 17, 2006 page 130 of 926
REJ09B0283-0300
* The synchronous DRAM interface is not supported in the H8S/2678 Group.
Bit Name
W22
W21
W20
Initial Value
1
1
1
R/W
R/W
R/W
R/W
Description
Area 2 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 2 while AST2 bit in
ASTCR = 1.
A CAS latency is set when the synchronous
DRAM is connected * . The setting of area 2 is
reflected to the setting of areas 2 to 5. A CAS
latency can be set regardless of whether or not
an ASTCR wait state insertion is enabled.
000:
001:
010:
011:
100:
101:
110:
111:
000:
001:
010:
011:
1XXX: Setting prohibited.
Program wait not inserted
1 program wait state inserted
2 program wait states inserted
3 program wait states inserted
4 program wait states inserted
5 program wait states inserted
6 program wait states inserted
7 program wait states inserted
Synchronous DRAM of CAS latency 1 is
connected to areas 2 to 5.
Synchronous DRAM of CAS latency 2 is
connected to areas 2 to 5.
Synchronous DRAM of CAS latency 3 is
connected to areas 2 to 5.
Synchronous DRAM of CAS latency 4 is
connected to areas 2 to 5.

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