D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 412

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 8 EXDMA Controller
The source address repeat area is specified by bits SARA4 to SARA0 in EDACR, and the
destination address repeat area by bits DARA4 to DARA0 in EDACR. The size of each repeat
area can be specified independently.
When the address register value is the last address in the repeat area and repeat area overflow
occurs, DMA transfer can be temporarily halted and an interrupt request sent to the CPU. If the
SARIE bit in EDACR is set to 1, when the source address register overflows the repeat area, the
IRF bit is set to 1 and the EDA bit cleared to 0 in EDMDR, and transfer is terminated. If EDIE = 1
in EDMDR, an interrupt is requested. If the DARIE bit in EDACR is set to 1, the above applies to
the destination address register.
If the EDA bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 8.9
illustrates the operation of the repeat area function.
Caution is required when the repeat area overflow interrupt function is used together with block
transfer mode. If transfer is always terminated when repeat area overflow occurs in block transfer
Rev. 3.00 Mar 17, 2006 page 360 of 926
REJ09B0283-0300
When lower 3 bits (8-byte area) of EDSAR are designated as repeat area
(SARA4 to SARA0 = 3)
Figure 8.9 Example of Repeat Area Function Operation
External memory
H'23FFFE
H'23FFFF
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
H'240008
H'240009
:
:
EDSAR values
Range of
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
Repeated
Repeat area overflow
interrupt can be
requested

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