D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 202

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 6 Bus Controller (BSC)
Bit
11
10
9
8
7
6
Rev. 3.00 Mar 17, 2006 page 150 of 926
REJ09B0283-0300
Bit Name
RTCK2
RTCK1
RTCK0
RFSHE
CBRM
Initial Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Refresh Control
Description
Reserved
This bit can be read from or written to.
However, the write value should always be 0.
Refresh Counter Clock Select
These bits select the clock to be used to
increment the refresh counter. When the input
clock is selected with bits RTCK2 to RTCK0,
the refresh counter begins counting up.
000: Count operation halted
001: Count on /2
010: Count on /8
011: Count on /32
100: Count on /128
101: Count on /512
110: Count on /2048
111: Count on /4096
Refresh control can be performed. When
refresh control is not performed, the refresh
timer can be used as an interval timer.
0: Refresh control is not performed
1: Refresh control is performed
CBR Refresh Control
Selects CBR refreshing performed in parallel
with other external accesses, or execution of
CBR refreshing alone.
When the continuous synchronous DRAM
space is set, this bit can be read/written, but the
setting contents do not affect operations.
0: External access during CAS-before-RAS
1: External access during CAS-before-RAS
refreshing is enabled
refreshing is disabled

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