D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 34

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

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Rev. 3.00 Mar 17, 2006 page xxxii of l
Example of Access Timing when RAS Signal Goes Low from Beginning
of T
Example of Timing with One Row Address Output Maintenance State
(RAST = 0, CAST = 0) ........................................................................................ 179
Example of Timing with Two-State Precharge Cycle (RAST = 0, CAST = 0) ... 180
Example of Wait State Insertion Timing (2-State Column Address Output)....... 182
Example of Wait State Insertion Timing (3-State Column Address Output)....... 183
2-CAS Control Timing (Upper Byte Write Access: RAST = 0, CAST = 0) ....... 184
Example of 2-CAS DRAM Connection............................................................... 185
Operation Timing in Fast Page Mode (RAST = 0, CAST = 0)............................ 186
Operation Timing in Fast Page Mode (RAST = 0, CAST = 1)............................ 187
Example of Operation Timing in RAS Down Mode (RAST = 0, CAST = 0) ..... 188
Example of Operation Timing in RAS Up Mode (RAST = 0, CAST = 0) .......... 189
RTCNT Operation ............................................................................................... 190
Compare Match Timing....................................................................................... 191
CBR Refresh Timing ........................................................................................... 191
CBR Refresh Timing (RCW1 = 0, RCW0 = 1, RLW1 = 0, RLW0 = 0) ............. 192
Example of CBR Refresh Timing (CBRM = 1)................................................... 193
Self-Refresh Timing............................................................................................. 194
Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States............................................................................................................ 195
Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1
(RAST = 0, CAST = 0) ........................................................................................ 196
Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0
(RAST = 0, CAST = 1) ........................................................................................ 197
Relationship between and SDRAM
(when PLL frequency multiplication factor is 1 or 2) ..................................... 202
Basic Access Timing of Synchronous DRAM (CAS Latency 1)......................... 203
CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) ........................... 205
Example of Access Timing when Row Address Output Hold State Is 1 State
(RCD1 = 0, RCD0 = 1, SDWCD = 0, CAS Latency 2) ....................................... 207
Example of Timing with Two-State Precharge Cycle
(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)......................................... 209
Example of Write Access Timing when CAS Latency Control Cycle Is
Disabled (SDWCD = 1) ....................................................................................... 210
DQMU and DQML Control Timing
(Upper Byte Write Access: SDWCD = 0, CAS Latency 2)................................. 211
DQMU and DQML Control Timing
(Lower Byte Read Access: CAS Latency 2)........................................................ 212
Example of DQMU and DQML Byte Control..................................................... 213
Operation Timing of Burst Access (BE = 1, SDWCD = 0, CAS Latency 2)....... 215
r
State (CAST = 0) ......................................................................................... 178