D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 190
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 6 Bus Controller (BSC)
6.3.8
DRAMCR is used to make DRAM/synchronous DRAM * interface settings.
Note: * The synchronous DRAM interface is not supported in the H8S/2678 Group.
Bit
15
14
13
Rev. 3.00 Mar 17, 2006 page 138 of 926
REJ09B0283-0300
Bit Name
OEE
RAST
—
DRAM Control Register (DRAMCR)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
OE Output Enable
The OE signal used when EDO page mode
DRAM is connected can be output from the
(OE) pin. The OE signal is common to all areas
designated as DRAM space.
When the synchronous DRAM is connected,
the CKE signal can be output from the (OE) pin.
The CKE signal is common to the continuous
synchronous DRAM space.
0: OE/CKE signal output disabled
1: OE/CKE signal output enabled
RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS
signal is asserted from the start of the T
(rising edge of ) or from the falling edge of .
Figure 6.4 shows the relationship between the
RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas
designated as DRAM space.
0: RAS is asserted from
1: RAS is asserted from start of T
Reserved
This bit can be read from or written to.
However, the write value should always be 0.
(OE)/(CKE) pin can be used as I/O port
cycle
falling edge in T
r
cycle
r
cycle
r
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