D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 112

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 3 MCU Operating Modes
Bit
3
2
1
0
Note:
Rev. 3.00 Mar 17, 2006 page 60 of 926
REJ09B0283-0300
Bit Name
FLSHE
—
EXPE
RAME
* Mode 3 is available only in the F-ZTAT version of H8S/2678R Group.
Initial Value
0
0
—
1
R/W
R/W
—
R/W
R/W
Descriptions
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMCR2, EBR1, and EBR2). If
this bit is set to 1, the flash memory control registers
can be read/written to. If this bit is cleared to 0, the
flash memory control registers are not selected. At
this time, the contents of the flash memory control
registers are maintained. This bit should be written to
0 other than flash memory version.
0: Flash memory control registers are not selected
1: Flash memory control registers are selected for
Reserved
This bit is always read as 0 and cannot be modified.
External Bus Mode Enable
Sets external bus mode.
In modes 1, 2, and 4 to 6, this bit is fixed at 1 and
cannot be modified. In mode 3 * and 7, this bit has an
initial value of 0, and can be read and written.
Writing of 0 to EXPE when its value is 1 should only
be carried out when an external bus cycle is not
being executed.
0: External bus disabled
1: External bus enabled
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
for area H'FFFFC8 to H'FFFFCB
area H'FFFFC8 to H'FFFFCB